RTL Design (all experience range)

## About Tylsemi Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution. ## Role Overview As an RTL Design Engineer at Tylsemi, you will design, integrate, and deliver production-quality digital IP and SoC subsystems across a range of high-speed interconnect and chiplet-centric architectures. This role is open across experience levels (0–30 years): from engineers building strong RTL fundamentals to senior technical leaders driving architecture, quality, and execution across multiple programs. You’ll collaborate closely with architecture, verification, physical design, DFT, firmware, and validation teams to ensure clean, scalable implementations that meet performance, power, area, and schedule targets. ## What You’ll Do

• Implement and integrate RTL for SoC/IP blocks and subsystems (scope aligned to experience level)
• Design and integrate high-speed interfaces and fabrics such as UCIe, PCIe, Ethernet, and chiplet interconnect subsystems
• Contribute to RISC-V based subsystem integration (cores, interconnect, interrupts, debug, coherency/IO as applicable)
• Translate architecture and micro-architecture specs into clean, synthesizable RTL with clear interfaces and configurability
• Own block-level integration: register maps, address decoding, clock/reset strategy, CDC/RDC considerations, and low-power intent alignment
• Partner with verification to define test plans, close functional coverage, and debug simulation/formal failures efficiently
• Drive quality and signoff readiness: lint, CDC, synthesis checks, X-prop, reset/clock sanity, and review-friendly documentation
• Support timing/power/area closure with physical design: constraints awareness, pipeline tradeoffs, and implementation-friendly RTL
• Debug integration issues across the stack (RTL ↔ DV ↔ firmware ↔ emulation/FPGA ↔ silicon bring-up) and drive root-cause closure
• Contribute to reusable design methodology: templates, checklists, coding guidelines, and automation (Python/Tcl/Make or equivalent)

## What We’re Looking For

• Strong digital design fundamentals and ability to write correct, maintainable, synthesizable RTL (Verilog/SystemVerilog)
• Experience (or strong interest) in one or more of: UCIe, PCIe, Ethernet, chiplets, RISC-V subsystem integration
• Comfort working from specs and turning ambiguous requirements into crisp interfaces, assumptions, and implementation plans
• Debug mindset: structured problem statements, waveform/log driven analysis, and clear closure plans
• Good engineering hygiene: readable code, meaningful reviews, reproducible results, and concise documentation
• Ability to collaborate across architecture, DV, PD, DFT, and software teams to drive predictable execution

## Required Skills

• RTL design
• UCIe
• PCIe
• Chiplets
• RISC-V
• Ethernet

## Nice to Have

• SoC integration experience: interconnects, memory-mapped IO, interrupts, DMA, and register modeling
• Low-power design exposure (clock gating, power states, UPF/CPF awareness) and reset/boot sequencing considerations
• CDC/RDC best practices and familiarity with lint/CDC/formal/synthesis flows
• Experience with performance/area/power tradeoffs and writing implementation-friendly RTL for timing closure
• Bring-up support experience (emulation/FPGA prototyping, post-silicon debug, firmware collaboration)

## Success in This Role Looks Like

• RTL that is correct, reviewable, and integration-ready with minimal late-stage surprises
• Predictable closure across lint/CDC/synthesis and smooth handoff to physical design and verification
• High-quality interface/IP integration (UCIe/PCIe/Ethernet/chiplet subsystems) with clear documentation and ownership
• Fast, data-driven debug and strong cross-team alignment from early design through tapeout and bring-up
• Reusable methodology improvements that increase team velocity and reduce recurring issues

## Location

• Bengaluru, India
• Hyderābād, India
• New Delhi, India
• Pune, India

## Experience 0–30 years (level and scope will be aligned to your experience and strengths).